Random access memory devices for storing digital data have usually taken the form of integrated circuit devices having thousands of memory cells. The memory cells in the past have been formed with capacitors to hold an electrical charge representative of a bit of data, and numerous transistor and diode structures associated with each cell to access the data. The ability to provide more memory cells in a given area has been directly related to the ability to form smaller and smaller structures using photolithography and other common processes and to improvements in reducing the amount of access circuitry associated with each cell. X-ray lithography promises smaller structures, but is far from becoming practical. Another option is to stack layers of memory cells on top of one another. A problem with stacking arises from the use of high temperatures to form the subsequent layers. The high temperatures cause the previous layers to continue to change. Dopants used in the formation of the previous layers continue to diffuse under such high temperatures, making it very difficult to keep the memory cells in earlier formed layers from becoming defective.
One solution to this problem is seen in U.S. Pat. No. 5,375,085 to Gnade et al. Rather than using the standard transistors and capacitive electrical charge to represent digital data, Gnade et al. uses the magnetization of ferroelectric material in a three dimensional semiconductor structure. As seen in prior art FIG. 1, which corresponds to FIG. 4 in the Gnade et al. patent, a first set of parallel conductors 14a, 14b, 14c, are arranged perpendicularly to a second set of parallel conductors indicated at 18 over a semiconductor substrate 12. A layer of ferroelectric material 16 is deposited between the sets of conductors. When an electrical voltage is applied to a conductor in each layer, the ferroelectric material between the overlap of the conductors forms a capacitor which retains an electrical polarization whose orientation is representative of a bit of data. The orientation of the polarization affects the value of the capacitance between the conductors. Data stored in a cell can be determined by applying an electric voltage, and detecting the difference in capacitance caused by different polarization orientations of the cell. Multiple layers of conductors and ferroelectric material are formed without adversely affecting previous layers, providing a three dimensional storage device.
A problem with the three dimensional storage device described above is that the ferroelectric material is deposited between the lower set of conductors, resulting in significant capacitive loading between adjacent conductors. If the loading is too great, the polarization of the ferroelectric material may not be sufficient to generate a readable signal, resulting in corruption of data in the storage device. There is a need for providing three dimensional ferroelectric semiconductor memory devices with minimal capacitive loading between adjacent cells to permit the accurate reading and writing of data.
To read data from a cell, prior ferroelectric storage devices associated an access transistor with each cell to couple the cell to its bit line. Some cells contain two ferroelectric capacitors and two access transistors with one functioning as a reference. The ferroelectric capacitors within each memory cell receive complementary input signals such that the ferroelectric capacitors are polarized in opposite states to indicate a 1 or a 0. When the pairs of capacitors for each cell are read, a resulting voltage on the bit lines, which result from applying a pulse on a plate line, is compared using a differential sense amplifier to compare the voltages on the bit lines and thus determine the polarity on the ferroelectric capacitors within the cell. Having an access transistor for each cell added considerable volume to the size of each cell, reducing the overall cell density obtainable for a ferroelectric storage device. There is a need for a simple access circuit that can sense the data in a cell, and rewrite the data in the same memory access cycle.
While the density of memory cells in three dimensional ferroelectric storage devices is much higher than that of conventional semiconductor memories, the circuitry used to access the memory cells still requires much real estate on the semiconductor substrate. As seen in Gnade et al., the read/write circuitry is positioned adjacent the three dimensional memory cell structure with conductors from the structure being coupled to the adjacent circuitry. There is a need to further increase the overall density of memory cells in storage devices, including the need to reduce the real estate needs of the access circuitry. There is yet a further need to provide electrical contacts to the access circuitry from the three dimensional ferroelectric storage device. In addition, the circuit must be capable of utilizing a reference cell in addition to the data cell without the use of a transistor for each cell.